DRAM Controller

The DRAM controller controls SDRAM access & timings.

  1. DRAM Controller
  2. Driver sources
  3. Registers
    1. 0x00 CCR controller configuration register
    2. 0x04 DCR dram configuration register
    3. 0x08 IOCR i/o configuration register
    4. 0x0c CSR controller status register
    5. 0x10 DRR dram refresh register
    6. 0x14 TPR0 dram timing parameters register 0
    7. 0x18 TPR1 dram timing parameters register 1
    8. 0x1c TPR2 dram timing parameters register 2
    9. 0x20 GDLLCR global dll control register
    10. 0x4c RSLR0 rank system latency register
    11. 0x50 RSLR1 rank system latency register
    12. 0x5c RDGR0 rank dqs gating register
    13. 0x60 RDGR1 rank dqs gating register
    14. 0x98 ODTCR odt configuration register
    15. 0x9c DTR0 data training register 0
    16. 0xa0 DTR1 data training register 1
    17. 0xa4 DTAR data training address register
    18. 0xa8 ZQCR0 zq control register 0
    19. 0xac ZQCR1 zq control register 1
    20. 0xb0 ZQSR zq status register
    21. 0xb4 IDCR initializaton delay configure register
    22. 0x1f0 MR mode register
    23. 0x1f4 EMR extended mode register
    24. 0x1f8 EMR2 extended mode register
    25. 0x1fc EMR3 extended mode register
    26. 0x200 DLLCTR dll control register
    27. 0x204 DLLCR[5] dll control register
    28. 0x218 DQTR0 dq timing register
    29. 0x21c DQTR1 dq timing register
    30. 0x220 DQTR2 dq timing register
    31. 0x224 DQTR3 dq timing register
    32. 0x228 DQSTR dqs timing register
    33. 0x22c DQSBTR dqsb timing register
    34. 0x230 MCR mode configure register
    35. 0x23C POWER power control
    36. 0x240 APR arbiter period register
    37. 0x244 PLDTR priority level data threshold register
    38. 0x250 HPCR[32] host port configure register
    39. 0x2e0 CSEL controller select register

Driver sources

Registers

0x00 CCR controller configuration register

Bit #

  • 31 DRAM_INIT Set to 1 to initialize DRAM chip. Cleared when done.
  • 30 DATA_TRAINING Set to 1 to start data training. Cleared when done.
  • 28 ITM_DISABLE Set to 1 to disable Iterface Timing Module
  • 17 DQS_DRIFT_COMPENSATION
  • 14 DQS_GATE

0x04 DCR dram configuration register

Bit #

  • 13-14 MODE 1=INTERLEAVE
  • 12 CMD_ON_ALL_RANKS
  • 10-11 RANK
  • 6-8 BUS_WIDTH
  • 3-5 CHIP_DENSITY
  • 1-2 IO_WIDTH Bus I/O width / 8
  • 0 DRAM_TYPE 0=DDR2, 1=DDR3

0x08 IOCR i/o configuration register

Bit #:

  • 30-31 ODT_EN (normally not used, DDR2 feature?)
  • 0-29 UNKNOWN, set to 0x00cc0000

0x0c CSR controller status register

Bit #:

  • 20 DRAM_FAILED Set to 1 if DRAM training failed, after triggering CCR DATA_TRAINING

0x10 DRR dram refresh register

  • 24-31 UNKNOWN set to 0x8
  • 8- REFRESH_PERIOD_2 7987*clk/1024*9 - 200
  • 0-7 REFRESH_PERIOD_1 336*clk/1024, or 131*clk/1024 for smaller DRAM sizes

0x14 TPR0 dram timing parameters register 0

0x18 TPR1 dram timing parameters register 1

0x1c TPR2 dram timing parameters register 2

0x20 GDLLCR global dll control register

0x4c RSLR0 rank system latency register

0x50 RSLR1 rank system latency register

0x5c RDGR0 rank dqs gating register

0x60 RDGR1 rank dqs gating register

0x98 ODTCR odt configuration register

0x9c DTR0 data training register 0

0xa0 DTR1 data training register 1

0xa4 DTAR data training address register

0xa8 ZQCR0 zq control register 0

0xac ZQCR1 zq control register 1

0xb0 ZQSR zq status register

0xb4 IDCR initializaton delay configure register

0x1f0 MR mode register

0x1f4 EMR extended mode register

0x1f8 EMR2 extended mode register

0x1fc EMR3 extended mode register

0x200 DLLCTR dll control register

0x204 DLLCR[5] dll control register

Bit #

  • 31 0x80000000 ENABLE
  • 30 0x40000000 nRESET

0x218 DQTR0 dq timing register

0x21c DQTR1 dq timing register

0x220 DQTR2 dq timing register

0x224 DQTR3 dq timing register

0x228 DQSTR dqs timing register

0x22c DQSBTR dqsb timing register

0x230 MCR mode configure register

0x23C POWER power control

Bit #

  • 0 0x00000001 PAD_HOLD When this bit is set to 1, all the output state of DRAM pad is hold.

0x240 APR arbiter period register

0x244 PLDTR priority level data threshold register

0x250 HPCR[32] host port configure register

unsigned int    AcsEn:1;    //bit0, host port access enable
unsigned int    reserved0:1;    //bit1
unsigned int    PrioLevel:2;    //bit2, host port poriority level
unsigned int    WaitState:4;    //bit4, host port wait state
unsigned int    CmdNum:8;       //bit8, host port command number
unsigned int    reserved1:14;   //bit16
unsigned int    WrCntEn:1;      //bit30, host port write counter enable
unsigned int    RdCntEn:1;      //bit31, host port read counter enable

DRAM_HOST_USB1  = 4,
DRAM_HOST_USB2  = 5,
DRAM_HOST_CPU   = 16,
DRAM_HOST_GPU   = 17,
DRAM_HOST_BE    = 18,
DRAM_HOST_FE    = 19,
DRAM_HOST_CSI   = 20,
DRAM_HOST_TSDM  = 21,
DRAM_HOST_VE    = 22,
DRAM_HOST_USB   = 24,
DRAM_HOST_NDMA  = 25,
DRAM_HOST_ATH   = 26,
DRAM_HOST_IEP   = 27,
DRAM_HOST_SDHC  = 28,
DRAM_HOST_DDMA  = 29,
DRAM_HOST_GPS   = 30,

0x2e0 CSEL controller select register

Set to 0x16237495 on sun4i to enable the controller. Unused on sun5i.