MMC Controller

The MMC controller manages access to SD/NNC/eMMC storage devices

Driver sources

Registers

(0x00) gctrl; SMC Global Control Register

(0x04) clkcr; SMC Clock Control Register

(0x08) timeout; SMC Time Out Register

(0x0C) width; SMC Bus Width Register

(0x10) blksz; SMC Block Size Register

(0x14) bytecnt; SMC Byte Count Register

(0x18) cmd; SMC Command Register

(0x1C) arg; SMC Argument Register

(0x20) resp0; SMC Response Register 0

(0x24) resp1; SMC Response Register 1

(0x28) resp2; SMC Response Register 2

(0x2C) resp3; SMC Response Register 3

(0x30) imask; SMC Interrupt Mask Register

(0x34) mint; SMC Masked Interrupt Status Register

(0x38) rint; SMC Raw Interrupt Status Register

(0x3C) status; SMC Status Register

(0x40) ftrglevel; SMC FIFO Threshold Watermark Register

(0x44) funcsel; SMC Function Select Register

(0x48) cbcr; SMC CIU Byte Count Register

(0x4C) bbcr; SMC BIU Byte Count Register

(0x50) dbgc; SMC Debug Enable Register

(0x54~0x7c) res0[11];

(0x80) dmac; SMC IDMAC Control Register

(0x84) dlba; SMC IDMAC Descriptor List Base Address Register

(0x88) idst; SMC IDMAC Status Register

(0x8C) idie; SMC IDMAC Interrupt Enable Register

(0x90) chda;

(0x94) cbda;

(0x98~0xff) res1[26];

(0x100) fifo; SMC FIFO Access Address

RAM area for command fifo

0xXXXX REGISTERNAME2

description ..

Bit #

  • 7 0x80 ISO_UPDATE_EN (Device only)
  • 6 0x40 SOFT_CONNECT (Device only)
  • 5 0x20 HIGH_SPEED_EN
  • 4 0x10 HIGH_SPEED_FLAG
  • 3 0x08 RESET
  • 2 0x04 RESUME
  • 1 0x02 SUSPEND
  • 0 0x01 SUSPEND_ENBit #

0x0008 ....