Security Subsystem

The Security Subsustem contains a random number generator and crypto support for a number of cryptographic algorithms.

  • AES, DES, 3DES crypto with ECB, CBC, CNT modes
  • SHA-1, MD5 message digst
  • 128-bits, 192-bits and 256-bits key size for AES
  • 160-bits hardware PRNG with 192-bits seed (according to manual)
  • hardware 64-bit random generator (according to datasheet & manual overview)
  • 32-words RX FIFO and 32-words TX FIFO for high speed application
  • Both CPU mode and DMA mode
  1. Security Subsystem
  2. Driver sources
  3. Registers
    1. Initial register values
    2. After fill with ffffffff
    3. After fill with 00000000
  4. Interrupt
  5. Clocks

Driver sources

None

Registers

0x01c15000 - 0x01c15FFF

Details unknown.

Initial register values

01c15000: 00010000 00000000 00000000 00000000    ................
01c15010: 00000000 00000000 00000000 00000000    ................
01c15020: 00000000 00000000 00000000 00000000    ................
01c15030: 00000000 00000000 00000000 00000000    ................
01c15040: 00000000 60000f0f 00000000 00000000    .......`........

After fill with ffffffff

01c15000: 0f01fffd 00000000 00000000 00000000    ................
01c15010: 00000000 00000000 00000000 00000000    ................
01c15020: 00000000 ffffffff ffffffff ffffffff    ................
01c15030: ffffffff ffffffff ffffffff ffffffff    ................
01c15040: ffffffff 60001f1f 0000041f 00000000    .......`........

After fill with 00000000

01c15000: 00010004 00000000 00000000 00000000    ................
01c15010: 00000000 00000000 00000000 00000000    ................
01c15020: 00000000 00000000 00000000 00000000    ................
01c15030: 00000000 00000000 00000000 00000000    ................
01c15040: 00000000 60000000 00000000 00000000    .......`........

Interrupt

Interrupt #54

Clocks

0x01c20000 + offset

CCMUAHBCLKGATE0_REG0060 __u32 SsGate:1; //bit5, gating AHB clock for SS, 0-mask, 1-pass

volatile ccmumodule0clk_t SsClk; //0x009C, SS module clock control

typedef struct __CCMU_MODULE0_CLK
{
    __u32   ClkDiv:4;           //bit0,  clock divide ratio, divided by (m+1), 1~16 ex.
    __u32   reserved0:12;       //bit4,  reserved
    __u32   ClkPreDiv:2;        //bit16, clock pre-divide ratio, predivided by 2^n , 1/2/4/8 ex.
    __u32   reserved1:6;        //bit18, reserved
    __u32   ClkSrc:2;           //bit24, clock source select, 00-HOSC, 01-PLL6, 10-PLL5, 11-reserved
    __u32   reserved2:5;        //bit26, reserved
    __u32   SpecClkGate:1;      //bit31, Gating special clock, 0-CLOCK OFF, 1-CLOCK ON
 } __ccmu_module0_clk_t;