The QSOC812A is a proposed mass-volume modern SoC that is entirely Free-Software Programmable (no closed or undocumented hardware and no proprietary firmware required). The specifications will be as follows:
- 8 SMP RISC Cores using Tensilica Xtensa technology (TBD)
- 28nm and in excess of 1.2ghz Clock Rate (TBD)
- 34mm x 34mm Ultra-low-cost Thin Quad-Flat Packaging (304-pin, 0.4mm pitch)
- 32-bit-wide DDR2,3,4 and LPDDR2 RAM (DDR3 up to 2166mhz)
- NAND Flash (8-bit, 4-way concurrent) Controller
- USB-3, USB-OTG, USB-2, SATA-3
- 3x SPI, 3x SD/MMC
- 2x 2-lane PCIe v3.0 (reconfigurable to 1x 4-lane PCIe v3.0)
- 2x MIPI (4-lane), HDMI in, HDMI out, 1x 24-pin RGB/TTL, Dual-channel LVDS
- 3x SD/MMC (v4, UHS-II), 3x SPI, 3x I2C
- 4x PWM, 2x UART, IRDA, 4-wire Touchscreen Controller, 2x PS/2, CANBus
- SP-DIF, Analog Stereo Line-In, Stereo Headphones, AC97, I2S
- 2x MPEG Transport Stream Interfaces
- SIM Card Interface
Pinouts are carefully multiplexed by function group for particular market segments, making it possible to cover several product lines with a very low overall pincount in an ultra-low-cost package.
The unique selling point of the QSOC812A is its software-programmability combined with low power. The XTensa VLIW and DSP extension capabilities provide enough processing power to perform 1080p decode and 3D Graphics purely in software. XTensa's LX4 with Base-band DSP extensions at its highest configuration is capable of 100 Giga-MACs at 1ghz. This is roughly equivalent to the performance of an AMD Radeon HD 6250 GPU.
However this is just a single XTensa RISC core! 8 such RISC cores are planned, leaving some concerns to be addressed such as power consumption, die area etc. Based on public information so far obtained from Tensilica's web site the prospects look extremely good, thanks to the combination of 3-way VLIW and 8-way SIMD. The silicon area budget for the entire SoC is around 7sq.mm: this will define the upper limit of the chosen configuration.
Here are the questions that I would ask Teselica application engineers if I had to deal with them. First of all I will have an idea of workloads that I need. For example:
- For general processing - a workload equivalent to Tegra 2 CPU performance. How Xtensa compares to Tegra 2 CPU performance? What is the Xtensa configuration to catch up that level of performance?
- For video decoding - a workload equivalent to fixed unit of video decoding unit like in Allwinner 10. What is the Xtensa configuration to catch up that level of performance?
- For 3D graphics - a workload equivalent to Radeon 6250 GPU. What is the Xtensa configuration to catch up that level of performance?
- For base band... Then after lot of discussions, tests and simulations I suppose that I will have to decide on the right balance of features - number of cores, core clocks, caches, memory access speed and etc.
To the key selling point of Tensilica, programmability, I would have the following groups of questions:
- Can all of the optional pre-defined execution units co-exist simultaneously in one configuration? What is the price for the optional pre-defined execution units?
Optional pre-defined execution units as in page 2 of the Xtensa LX4 specifications are:
- 32-bit multiplier and/or 16-bit multiplier and MAC
- Single-precision floating point unit
- Double-precision floating point acceleration
- 3-way 64-bit VLIW (VLIW3)
- Pre-defined 32-bit GPIO and FIFO-like Queue interfaces
- Can all of the optional execution units for additional licensing co-exist simultaneously with optional pre-defined execution units in one configuration? Or they must substitute one or more of pre-defined units? For example if only one unit for additional licensing can exists per configuration and it occupies the 3-way 64-bit VLIW (VLIW3) unit, that means that if we want audio using VLIW we will have difficulties to implement 3D acceleration in the same core at the same time. And what is the price of the licenses?
Optional execution units for additional licensing according the Xtensa LX4 specifications are:
- ConnX Vectra LX DSP engine
- ConnX Vectra VMB for baseband acceleration
- ConnX D2 DSP engine
- ConnX BBE16 Baseband engines
- HiFi 2 and HiFi EP Audio engines
- Are the software/hardware development kits for programming and configuration of Xtensa freely available for developers? If not, what is the price?
Differences between XTensa and FPGA
- What is the difference between Xtensa and Xilinx Zynq/Altera Cyclone that have 28nm Dual-Core Cortex A9 with on-board FPGA? Both solutions have fixed part and programmable part. Both solutions use SystemC as description language. Xtensa claims that their solution is more close to software programmability than pure hardware programmability in FPGAs. But is this true?