NAND Controller

The NAND controller manages access to NAND chips

Driver sources

Data

Register base: 0x01c03000

Interrupt: 13

Registers

0x0000 CTL Control register

Bit #

  • 0 1 EN Enable controller
  • 1 1 RESET Reset controller (abort command). Automatically clears to 0 when complete.
  • 2 1 BUS_WIDTH 0 = 8-bit. Nothing else supported.
  • 3 1 RB_SEL RB line select, 0 or 1
  • 6 1 CE_CTL Force drive CE line
  • 7 1 CE_CTL1 Unused
  • 8 0xf PAGE_SIZE Chip page size, 0=?
  • 12 1 SAM ??
  • 14 1 RAM_METHOD If SRAM is accessed by CPU(0) or DMA(1)
  • 24 7 CE_SEL Which CE line to select
  • 31 1 DEBUG_CTL ??

0x0004 ST Status register

Bit #

  • 0 1 RB_B2R RB transition to R
  • 1 1 CMD_INT_FLAG CMD completed
  • 2 1 DMA_INT_FLAG DMA completed
  • 3 1 CMD_FIFO_STATUS FIFO ready to accept command
  • 4 1 STA ???
  • 5 1 NATCH_INT_FLAG ???
  • 8 1 RB_STATE0 RB line 0 state
  • 9 1 RB_STATE1 RB line 1 state
  • 10 1 RB_STATE2 Unused
  • 11 1 RB_STATE3 Unused

0x0008 INT Interrupt enable register

Bit #

  • 0 1 B2R_INT_ENABLE Enable B2R IRQ
  • 1 1 CMD_INT_ENABLE Enable CMD IRQ
  • 2 1 DMA_INT_ENABLE Enbale DMA IRQ

0x000C TIMING_CTL

0xf3f

0x0010 TIMING_CFG

0x3ffff

  • 0 0x3 DONE Delay after command
  • 12 0x3 CLE Delay before initial CLE

0x0014 ADDR_LOW

Low address bits, in host order

0x0018 ADDR_HIGH

High address bits, in host order

0x001C SECTOR_NUM

Number of sectors in page command operations

0x0020 CNT

0x3ff

Number of bytes to tansfer, 1-0x400 (0 = 0x400)

0x0024 CMD

Bit #

  • 0 0xff CMD1 Primary command byte
  • 8 0xff CMD_HIGH_BYTE UNUSED
  • 16 0x7 ADR_NUM Number of address cycles 1-8 (0 = 8)
  • 19 1 SEND_ADR Send address cycles
  • 20 1 ACCESS_DIR 0=READ, 1=WRITE
  • 21 1 DATA_TRANS Command includes data transfer
  • 22 1 SEND_CMD1 Send CMD1 in the command transaction
  • 23 1 WAIT_FLAG Wait for RB to indicate readiness before continuing
  • 24 1 SEND_CMD2 Send CMD2 in the command transaction. (reg 0x28 bits 0xff << 0)
  • 25 1 SEQ 0=Random access, 1=Sequential. Affects ECC layout in page commands. Sequential is data ecc data ecc ..., Random is data data ... ecc ecc ...
  • 26 1 DATA_SWAP_METHOD ???
  • 27 1 ROW_AUTO_INC ???
  • 28 1 SEND_CMD3 Send CMD3 in the command transaction. (reg 0x2c bits 0xff << 24)
  • 29 1 SEND_CMD4 Send CMD4 in the command transaction. (reg 0x2c bits 0xff << 16)
  • 30 3 CMD_TYPE 0 = Normal, 1 = ECC, 2 = PAGE (DMA only)

0x0028 RCMD_SET

Bit #

  • 0 0xff CMD2
  • 8 0xff RANDOM_READ_CMD0
  • 16 0xff RANDOM_READ_CMD1

RANDOM_READ_* commands are used in PAGE commands to seek within the page. Fetch sector of data, seek, fetch ECC, seek, Fetch next sector of data...

0x002C WCMD_SET

Bit #

  • 0 0xff PROGRAM_CMD
  • 8 0xff RANDOM_WRITE_CMD
  • 16 0xff READ_CMD0
  • 24 0xff READ_CMD1

0x0030 IO_DATA

DMA I/O register

0x0034 ECC_CTL

Bit #

  • 0 1 ECC_EN Enable ECC
  • 3 1 ECC_PIPELINE ???
  • 4 1 ECC_EXCEPTION ???
  • 5 1 ECC_BLOCK_SIZE ???
  • 9 1 RANDOM_EN Enable randomizer
  • 10 1 RANDOM_DIRECTION ???
  • 12 0xf ECC_MODE ECC mode/size/layout
  • 16 0x7fff RANDOM_SEED

0x0038 ECC_ST

ECC Status.

Contains one bit per sector indicating ECC failure (0 = OK, 1 = FAIL)

0x003C DEBUG

???

0x0040 ECC_CNT0

0x0044 ECC_CNT1

0x0048 ECC_CNT2

0x004C ECC_CNT3

ECC counters per sector. 8 bits per 1K sector.

0x0050 USER_DATA_BASE

Area where user data is collected from the ECC/OOB data. 32 bits per 1k sector.

0x0090 EFNAND_STATUS

0x00A0 SPARE_AREA

Offset to the spare area?

0x00A4 PATTERN_ID

???

0x0400 RAM0_BASE

Transfer buffer for first sector

0x0800 RAM1_BASE

Transfer buffer for second sector

Boot block access

The boot blocks uses a special access mode not used for the rest of the NAND

  • RANDOM_SEED=0x4a80
  • SEQ mode access with sequential data and ecc layout (data, ecc, data, ecc, ...)
  • ECC_EN,ECC_PIPELINE,ECC_MODE=1

Randomizer

The controller includes a randomizer that scrambles the data to avoid large islands of the same charge. The randomizer seed is formed by page number % 128 as index into

static const unsigned short random_seed[128] = {
    0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72, 0x0d67, 0x67f9,
    0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436, 0x7922, 0x1510, 0x3860, 0x5287,
    0x480f, 0x4252, 0x1789, 0x5a2d, 0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e,
    0x5cb7, 0x7130, 0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56,
    0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55, 0x60f4, 0x728c,
    0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb, 0x6218, 0x79f3, 0x383f, 0x18d9,
    0x4f05, 0x5c82, 0x2912, 0x6f17, 0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2,
    0x542f, 0x4f62, 0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064,
    0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126, 0x1ca7, 0x1605,
    0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e, 0x2b7a, 0x1418, 0x1fd1, 0x7dc1,
    0x2d8e, 0x43af, 0x2267, 0x7da3, 0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3,
    0x42e6, 0x262b, 0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d,
    0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db
};