Allwinner A10 register guide
This page aims at documenting the known Allwinner A10 I/O registers. Any addresses in this document is using physical addressing.
How to contribute
Copy register information from headers in the kernel & u-boot sources, and hunt down what it means by reading how the registers are used in the sources.
Memory map sources
https://github.com/hno/uboot-allwinner/blob/sun4i/arch/arm/include/asm/arch-sunxi/cpu.hhttps://github.com/amery/linux-allwinner/blob/allwinner-v3.0-android-v2/arch/arm/mach-sun4i/include/mach/platform.h
Memory map
0x00000000-0x00003fff 16KB?SRAM A10x00004000-0x00007fff 16KB?SRAM A20x00008000-0x0000b3ff 13KB?SRAM A30x0000b400-0x0000bfff 3KB?SRAM A40x01c00000-0x1c00ffff 64KB?SRAM B (secure)0x01c00000-?????????? ??KB?SRAM D0x01c00000-0x3fffffff ??KBI/O0x01c00000-0x1c000fff 4KB?SRAMC0x01c01000-0x1c001fff 4KBDRAMC0x01c02000-0x1c002fff 4KB?DMA0x01c03000-0x1c003fff 4KBNAND0x01c04000-0x1c004fff 4KB?TS0X01C05000-0X01C05fff 4KB?SPI00X01C06000-0X01C06fff 4KB?SPI10X01C07000-0X01C07fff 4KB?MS0X01C08000-0X01C08fff 4KB?TVD0X01C09000-0X01C09fff 4KB?CSI00X01C0A000-0X01C0Afff 4KB?TVE00X01C0B000EMAC Ethernet Controller0X01C0C000?LCD00X01C0D000?LCD10X01C0E000VE0X01C0F000MMC00X01C10000MMC10X01C11000MMC20X01C12000MMC30X01C13000USB0 USB2.0 OTG Controller0X01C14000USB1 USB2.0 HOST Controller0X01C15000SS0X01C16000?HDMI0X01C17000?SPI20X01C18000SATA0X01C19000?PATA0X01C1A000?ACE0X01C1B000?TVE10X01C1C000USB2 USB2.0 HOST Controller0X01C1D000?CSI10X01C1E000?TZASC0X01C1F000?SPI30X01C20000CCM0X01C20400?INTC0X01C20800?PIO0X01C20C00TIMER0X01C21000?SPDIF0X01C21400?AC970X01C21800?IR00X01C21C00?IR10X01C22400?IIS0X01C22800?LRADC0X01C22C00?AD DA0X01C23000?KEYPAD0X01C23400?TZPC0X01C23800?SID0X01C23C00?SJTAG0X01C25000?TP0X01C25400?PMU0X01C28000UART00X01C28400UART10X01C28800UART20X01C28C00UART30X01C29000UART40X01C29400UART50X01C29800UART60X01C29C00UART70X01C2A000?PS200X01C2A400?PS210X01C2AC00?TWI00X01C2B000?TWI10X01C2B400?TWI20X01C2BC00?CAN0X01C2C400?SCR0X01C30000?GPS0X01C40000?MALI4000X01D00000?SRAM C /* module sram */0X01E00000?DE FE00X01E20000?DE FE10X01E60000?DE BE00X01E40000?DE BE10X01E80000?MP0X01EA0000?AVG0X3F500000?CSDM /* CoreSight Debug Module*/0x40000000-0xbfffffff 2GBSDRAM0xffff0000-0xffff8fff 32KB?BROM
SUNXI_CPU_CFG = (SUNXI_TIMER_BASE + 0x13c)
I/O Controllers
- ?SRAMC
- DRAMC
- ?DMA
- NAND
- ?TSI
- ?SPI
- ?MSCC
- ?TVD
- ?CSI
- ?TVE
- EMAC
- ?TCON
- VE
- ?SDC
- USB
- SS
- ?HDMI
- SATA
- ?PATA
- ?ACE
- ?TZASC
- CCM
- ?INT
- ?PORTC
- ?TIMERC
- ?SPDIF
- ?AC97
- ?IR
- ?IIS
- ?LRADC
- ?ADDA
- ?KEYPAD
- ?TZPC
- ?SID
- ?SJTAG
- ?TP
- ?PMU
- UART
- ?PS2
- ?TWI
- ?CAN
- ?SCR
- ?GPS
- ?MALI
- ?DEFE
- ?DEBE
- ?MP
- ?AVG
- ?BROM
- ?SDRAM
edittemplate A10 registers registered for A10_register_guide/*