A10 SATA controller
The SATA controller is an AHCI controller with some small twists.
The code can be found here: https://github.com/amery/linux-allwinner/commit/5080a650d1c91e6da2f29d4480bbf7e44b08cfad
From the driver code the only hw specific changes seems to be
- PHY control driver
- DMA setup using vendor specified port register 0x70 (SW_AHCI_PORT_DMA in the code) setting bits 8-15 to ox44 before each DMA transfer.
AHCI Controller Registers
0x00A0 BISTAFR
0x00A4 BISTCR
0x00A8 BISTFCTR
0x00AC BISTSR
0x00B0 BISTDECR
0x00B4 DIAGNR
0x00B8 DIAGNR1
0x00BC OOBR
0x00C0 PHYCS0R
0x00C4 PHYCS1R
0x00C8 PHYCS2R
0x00E0 TIMER1MS
0x00E8 GPARAM1R
0x00EC GPARAM2R
0x00F0 PPARAMR
0x00F4 TESTR
0x00F8 VERSIONR
0x00FC IDR
0x00FC RWCR
PORT registers
Port 0 starts at 0x0100. All offsets below are relative to the port base.
0x70 DMACR
Related to DMA setup somehow. Code writes 0x44 in bits 8-16 before starting DMA transaction.